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Preliminary Technical Data
FEATURES
100 MSPS guaranteed sampling rate 100 dB two-tone SFDR with 30 MHz and 31 MHz 81.6 dB SNR with 30 MHz input (3.2 V p-p input, 80Msps) 90 dBc SFDR with30 MHz input (3.2 V p-p input, 80Msps) Excellent linearity DNL = 0.5 LSB typical INL = 3.0 LSB typical 2.3 W power dissipation 3.3 V and 5 V supply operation 2.0 V p-p to 3.2 V p-p differential full-scale input LVDS outputs (ANSI-644 compatible) or CMOS outputs Data format select (offset binary or twos compliment) Output clock available
16-Bit, 80/100 MSPS, A/D Converter AD9446
FUNCTIONAL BLOCK DIAGRAM
AGND AVDD1 AVDD2 DRGND DRVDD DFS DCS MODE OUTPUT MODE
AD9446
VIN+ VINBUFFER
T/H
PIPELINE ADC
16 OR LVDS
CMOS
OUTPUT STAGING
2 32
OR D15D0 DCO
CLK+ CLK-
CLOCK &TIMING MANAGEMENT
REF
2
VREF SENSE REFT REFB
Figure 1.
APPLICATIONS
Multicarrier, multimode cellular receivers Antenna array positioning Power amplifier linearization Broadband wireless Radar Infrared imaging Communications instrumentation
Optional features allow users to implement various selectable operating conditions, including data format select and output data mode. The AD9446 is available in a 100-lead surface-mount plastic package (100-lead TQFP/EP) specified over the industrial temperature range -40C to +85C.
PRODUCT HIGHLIGHTS
1. True 16 bit linearity. 2. High performance: outstanding SFDR performance for multicarrier, multimode 3G and 4G cellular base station receivers. 3. Ease of use: on-chip reference and track-and-hold. An output clock simplifies data capture. 4. Packaged in a Pb-free, 100-lead TQFP/EP. 5. Clock duty cycle stabilizer (DCS) maintains overall ADC performance over a wide range of clock pulse widths. 6. OR (out-of-range) outputs indicate when the signal is beyond the selected input range.
GENERAL DESCRIPTION
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The AD9446 is a 16-bit monolithic, sampling analog-to-digital converter (ADC) with an on-chip track-and-hold circuit. It is optimized for power, small size, and ease of use. The product operates at up to a 100 MSPS conversion rate and is optimized for multicarrier, multimode receivers, such as those found in cellular infrastructure equipment. The ADC requires 3.3 V and 5.0 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are LVDS-compatible (ANSI644) or CMOS-compatible and include the means to reduce the overall current needed for short trace distances.
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Rev. PrF
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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AD9446 TABLE OF CONTENTS
DC Specifications ............................................................................. 3 AC Specifications.............................................................................. 4 Digital Specifications........................................................................ 6 Switching Specifications .................................................................. 7 Explanation of Test Levels ........................................................... 8 Absolute Maximum Ratings............................................................ 9 Thermal Resistance ...................................................................... 9 ESD Caution.................................................................................. 9 Definitions of Specifications ......................................................... 10 Pin Configurations and Function Descriptions ......................... 11 Equivalent Circuits ......................................................................... 16
Preliminary Technical Data
Typical Performance Characteristics ........................................... 17 Theory of Operation ...................................................................... 18 Analog Input and Reference Overview ................................... 18 Clock Input Considerations...................................................... 20 Power Considerations................................................................ 21 Digital Outputs ........................................................................... 21 Timing ......................................................................................... 21 Operational Mode Selection ..................................................... 21 Evaluation Board ........................................................................ 22 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 23
REVISION HISTORY
5/05--PrF: Preliminary Version
Rev. PrF | Page 2 of 24
Preliminary Technical Data DC SPECIFICATIONS
AD9446
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sampling rate, 3.2 V p-p differential input, internal trimmed reference (1.6 V mode), AIN = -1.0 dBFS, DCS on, unless otherwise noted. Table 1.
Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error1 Differential Nonlinearity (DNL)2 Integral Nonlinearity (INL)2 TEMPERATURE DRIFT Offset Error Gain Error VOLTAGE REFERENCE Output Voltage1 (VREF = 1.6 V) (VREF = 1.0 V) Load Regulation @ 1.0 mA Reference Input Current (External 1.6 V Reference) INPUT REFERRED NOISE ANALOG INPUT Input Span (VREF = 1.6 V) (VREF = 1.0 V) Input Common-Mode Voltage Input Resistance3 Input Capacitance3 POWER SUPPLIES Supply Voltage AVDD1 AVDD2 DRVDD--LVDS Outputs DRVDD--CMOS Outputs Supply Current AVDD1 AVDD22 IDRVDD2--LVDS Outputs IDRVDD2--CMOS Outputs PSRR Offset Gain POWER CONSUMPTION DC Input--LVDS Outputs DC Input--CMOS Outputs
1 2
Temp Full Full Full Full Full 25C Full Full Full Full Full Full Full 25C Full Full Full Full Full
Test Level VI VI VI VI VI I VI V V VI VI V VI V V V V V V
Min
AD9446BSVZ-80 Typ Max
Min
AD9446BSVZ-100 Typ Max 16 Guaranteed
0.3 0.5 3.0
Unit Bits
Guaranteed
0.3 0.5 3.0
1.5
mV % FSR LSB LSB LSB V/C %FS/C
1.6
1.0 2
1.6 1.0 2
V V mV A LSB rms V p-p V p-p V k pF
2.50 3.2
2.0 3.5 1 2.5
2.75 3.2 2.0 3.5 1 2.5
Full Full Full Full Full Full Full Full Full Full Full Full
IV IV IV IV VI VI VI V V V VI V
3.14 4.75
3.0 3.0
3.3
5.0 3.3
3.46
5.25 3.6 3.6
3.14 4.75 3.0 3.0
3.3 5.0 3.3 366 220 65 14 1 0.2 2.5 2.3
3.46 5.25 3.6 3.6
V V V V mA mA mA mA mV/V %/V W W
338 209 65
14
1
0.2
2.3 2.1
The internal voltage reference is trimmed at final test to minimize the gain error of the AD9446. Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 differential termination on each pair of output bits for LVDS output mode and approximately 5 pF loading on each output bit for CMOS output mode. 3 Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure.
Rev. PrF | Page 3 of 24
AD9446 AC SPECIFICATIONS
Preliminary Technical Data
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sample rate, 3.2 V p-p differential input, internal trimmed reference (1.6 V mode), AIN = -1 dBFS, DCS on, unless otherwise noted. Table 2.
Parameter SIGNAL-TO-NOISE RATIO (SNR) fIN = 10 MHz fIN = 10 MHz (2 V p-p Input) fIN = 35 MHz fIN = 70 MHz fIN = 100 MHz SIGNAL-TO-NOISE AND DISTORTION fIN = 10 MHz fIN = 10 MHz (2 V p-p Input) fIN = 35 MHz fIN = 70 MHz fIN = 100 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz fIN = 35 MHz fIN = 70 MHz fIN = 100 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 10 MHz fIN = 10 MHz (2 V p-p) fIN = 35 MHz fIN = 70 MHz fIN = 100 MHz WORST HARMONIC, SECOND OR THIRD fIN = 10 MHz fIN = 10 MHz (2 V p-p) fIN = 35 MHz fIN = 70 MHz fIN = 100 MHz Temp 25C Full 25C Full 25C Full 25C Full 25C 25C Full 25C Full 25C Full 25C Full 25C 25C 25C 25C 25C 25C Full 25C Full 25C Full 25C Full 25C 25C Full 25C Full 25C Full 25C Full 25C Test Level IV IV IV IV I IV IV IV V IV IV IV IV I IV IV IV V V V V V IV IV IV IV I IV IV IV V IV IV IV IV I IV IV IV V Min AD9446BSVZ-80 Typ Max 81.9 77.5 81.6 80.3 78.5 80.9 77.3 80.7 78.7 78.0 13.2 13.1 13.1 12.7 90 90 90 83 82 -90 -90 -90 -83 -82 Min AD9446BSVZ-100 Typ Max 79.6 76 79.5 79.0 78.6 78.9 75.5 78.5 77.2 76.6 13.0 12.9 12.7 12.6 90 90 88 84 82 -90 -90 -89 -84 -82 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
Rev. PrF | Page 4 of 24
Preliminary Technical Data
Parameter WORST SPUR EXCLUDING SECOND OR THIRD HARMONICS fIN = 10 MHz fIN = 10 MHz (2 V p-p) fIN = 35 MHz fIN = 70 MHz fIN = 100 MHz TWO-TONE SFDR fIN = 10.8 MHz @ -7 dBFS, 9.8 MHz @ -7 dBFS fIN = 70.3 MHz @ -7 dBFS, 69.3 MHz @ -7 dBFS ANALOG BANDWIDTH Temp Test Level Min AD9446BSVZ-80 Typ Max Min
AD9446
AD9446BSVZ-100 Typ Max Unit
25C Full 25C Full 25C Full 25C Full 25C 25C 25C Full
IV IV IV IV I IV IV IV V V V V
-95
-95 -90 -90 -85
-96 -95 -95 -95 -94 95
dBc dBc dBc dBc dBc dBc dBc dBc dBc dBFS dBFS
95
325
540
MHz
Rev. PrF | Page 5 of 24
AD9446 DIGITAL SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, RLVDSBIAS = 3.74 k, unless otherwise noted. Table 3.
Parameter CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE) High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance DIGITAL OUTPUT BITS--CMOS MODE (D0 to D13, OTR)1 DRVDD = 3.3 V High Level Output Voltage Low Level Output Voltage DIGITAL OUTPUT BITS--LVDS MODE (D0 to D13, OTR) VOD Differential Output Voltage2 VOS Output Offset Voltage CLOCK INPUTS (CLK+, CLK-) Differential Input Voltage Common-Mode Voltage Differential Input Resistance Differential Input Capacitance
1 2
Preliminary Technical Data
Temp Full Full Full Full Full
Test Level IV IV VI VI V
AD9446BSVZ-80 Min Typ Max 2.0 0.8 200
-10 2 +10
AD9446BSVZ-100 Min Typ Max 2.0 0.8 200 +10 2
Unit V V A A pF
-10
Full Full Full Full Full Full Full Full
IV IV VI VI IV VI V V
3.25 0.2 247 1.125 0.2 1.3 8 1.5 10 4 1.6 12 545 1.375
3.25 0.2 247 1.125 0.2 1.3 8 545 1.375
V V mV V V V k pF
1.5 10 4
1.6 12
Output voltage levels measured with 5 pF load on each output. LVDS RTERM = 100 .
Rev. PrF | Page 6 of 24
Preliminary Technical Data SWITCHING SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted. Table 4.
Parameter CLOCK INPUT PARAMETERS Maximum Conversion Rate Minimum Conversion Rate CLK Period CLK Pulse Width High1 (tCLKH) CLK Pulse Width Low1 (tCLKL) DATA OUTPUT PARAMETERS Output Propagation Delay--CMOS (tPD)2 (DX, DCO+) Output Propagation Delay--LVDS (tPD)3 (DX+, DCO+) Pipeline Delay (Latency) Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ)
1 2 3
AD9446
Temp Full Full Full Full Full Full Full Full Full Full
Test Level VI V V V V IV VI V V V
AD9446BSVZ-80 Min Typ Max 100 10 9.5 5.0 5.0 3.35 1.3 3.1 13 60 6
AD9446BSVZ-100 Min Typ Max 100 10 10 4.0 4.0 3.35 1.3 3.1 13 60 6
Unit
MSPS MSPS ns ns ns ns ns Cycles ns fs rms
With duty cycle stabilizer (DCS) enabled. Output propagation delay is measured from clock 50% transition to data 50% transition with 5 pF load. LVDS RTERM = 100 . Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.
N-1 AIN
N N+1
tCLKL tCLKH
1/fS CLK+ CLK-
tPD
DATA OUT N-12 N-11 12 CLOCK CYCLES DCO+ DCO-
05089-002
N
N+1
tCPD
Figure 2. LVDS Mode Timing Diagram
Rev. PrF | Page 7 of 24
AD9446
N-1 N N+1 VIN
Preliminary Technical Data
tCLKL tCLKH
CLK-
N+2
CLK+
tPD
12 CYCLES
DX
N-12
N-11
N-1
N
tDCOPD
DCO+ DCO-
05089-003
Figure 3. CMOS Timing Diagram
EXPLANATION OF TEST LEVELS
Test Level I II III IV V VI Definitions 100% production tested. 100% production tested at 25C and sample tested at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25C and guaranteed by design and characterization for industrial temperature range.
Rev. PrF | Page 8 of 24
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
Table 5.
With Respect to Parameter ELECTRICAL AVDD1 AGND AVDD2 AGND DRVDD DGND AGND DGND AVDD1 DRVDD AVDD2 DRVDD AVDD2 AVDD1 D0 to D13 DGND CLK, MODE AGND VIN+, VIN- AGND VREF AGND SENSE AGND REFT, REFB AGND ENVIRONMENTAL Storage Temperature Operating Temperature Range Lead Temperature Range (Soldering 10 sec) Junction Temperature Min -0.3 -0.3 -0.3 -0.3 -4 -4 -4 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -65 -40 Max +4 +6 +4 +0.3 +4 +6 +6 DRVDD + 0.3 AVDD1 + 0.3 AVDD2 + 0.3 AVDD1 + 0.3 AVDD1 + 0.3 AVDD1 + 0.3 +125 +85 300 150 Unit V V V V V V V V V V V V V C C C C
AD9446
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
The heat sink of the AD9446 package must be soldered to ground. Table 6.
Package Type 100-Lead TQFP/EP JA 19.8 JB 8.3 JC 2 Unit C/W
Typical JA = 19.8C/W (heat sink soldered) for multilayer board in still air. Typical JB = 8.3C/W (heat sink soldered) for multilayer board in still air. Typical JC = 2C/W (junction to exposed heat sink) represents the thermal resistance through heat sink path. Airflow increases heat dissipation, effectively reducing JA. Also, more metal directly in contact with the package leads, from metal traces through holes, ground, and power planes, reduces the JA. It is required that the exposed heat sink be soldered to the ground plane.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrF | Page 9 of 24
AD9446 DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth (Full Power Bandwidth) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay (tA) The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter, tJ) The sample-to-sample variation in aperture delay. Clock Pulse Width and Duty Cycle Pulse width high is the minimum amount of time that the clock pulse should be left in the Logic 1 state to achieve rated performance. Pulse width low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these specifications define an acceptable clock duty cycle. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 16-bit resolution indicates that all 65536 codes must be present over all operating ranges. Effective Number of Bits (ENOB) The effective number of bits for a sine wave input at a given input frequency can be calculated directly from its measured SINAD using the following formula:
Preliminary Technical Data
Minimum Conversion Rate The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Offset Error The major carry transition should occur for an analog value of 1/2 LSB below VIN+ = VIN-. Offset error is defined as the deviation of the actual transition from that point. Out-of-Range Recovery Time The time it takes for the ADC to reacquire the analog input after a transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. Output Propagation Delay (tPD) The delay between the clock rising edge and the time when all bits are within valid logic levels. Power-Supply Rejection Ratio The change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. Signal-to-Noise and Distortion (SINAD) The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. Signal-to-Noise Ratio (SNR) The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. SFDR may be reported in dBc (that is, degrades as signal level is lowered) or dBFS (always related back to converter full scale). Temperature Drift The temperature drift for offset error and gain error specifies the maximum change from the initial (25C) value to the value at TMIN or TMAX. Total Harmonic Distortion (THD) The ratio of the rms input signal amplitude to the rms value of the sum of the first six harmonic components. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product.
ENOB =
(SINAD - 1.76 )
6.02
Gain Error The first code transition should occur at an analog value of 1/2 LSB above negative full scale. The last transition should occur at an analog value of 1 1/2 LSB below the positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Integral Nonlinearity (INL) The deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSBs beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Maximum Conversion Rate The clock rate at which parametric testing is performed.
Rev. PrF | Page 10 of 24
Preliminary Technical Data PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
87 DRGND 88 DRVDD 76 DRVDD 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 AGND 42 AVDD1 43 AVDD1 44 AVDD1 45 AGND 46 DRGND 47 DRVDD 48 D0- 49 D0+ 50 97 AVDD1 96 AVDD1 95 AVDD1 94 AVDD1 93 AVDD1 92 AVDD1
AD9446
100 AGND
98 AGND
91 AGND
99 SFDR
86 D15+
84 D14+
82 D13+
80 D12+
78 D11+
85 D15-
83 D14-
81 D13-
79 D12-
DCS MODE DNC OUTPUT MODE DFS LVDS_BIAS AVDD1 SENSE VREF AGND REFT REFB AVDD2 AVDD2 AVDD2 AVDD2 AVDD2 AVDD2 AVDD1 AVDD1 AVDD1 AGND VIN+ VINAGND AVDD2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 AVDD2 26 AVDD2 27 AVDD2 28 AVDD2 29 AVDD2 30 AVDD2 31 AVDD1 32 AVDD1 33 AVDD1 34
77 D11-
90 OR+
89 OR-
AD9446 Pinout
DRGND D10+ D10D9+ D9D8+ D8DCO+ DCOD7+ D7DRVDD DRGND D6+ D6D5+ D5D4+ D4D3+ D3D2+ D2D1+ D1-
AVDD2 35
AVDD1 36
AVDD2 37
AVDD1 38
AGND 39
CLK+ 40
Figure 4. 100-Lead TQFP/EP Pin Configuration in LVDS Mode
Rev. PrF | Page 11 of 24
CLK- 41
AD9446
Table 7. Pin Function Descriptions--100-Lead TQFP/EP in LVDS Mode
Pin No. 1 2 3 4 5 6, 18 to 20, 32 to 34, 36, 38, 43 to 45, 92 to 97 7 8 9, 21, 24, 39, 42, 46, 91, 98, 100, Exposed Heat Sink 10 11 12 to 17, 25 to 31, 35, 37 22 23 40 41 47, 63, 75, 87, 48, 64, 76, 88 49 50 51 52 53 54 55 56 57 58 59 60 61 62 65 66 67 68 69 70 71 72 73 74 77 78 Mnemonic DCS MODE DNC OUTPUT MODE DFS LVDS_BIAS AVDD1 SENSE VREF AGND REFT REFB AVDD2 VIN+ VIN- CLK+ CLK- DRGND DRVDD D0- (LSB) D0+ D1- D1+ D2- D2+ D3- D3+ D4- D4+ D5- D5+ D6- D6+ D7- D7+ DCO- DCO+ D8- D8+ D9- D9+ D10- D10+ D11- D11+
Preliminary Technical Data
Description Clock Duty Cycle Stabilizer (DCS) Control Pin, CMOS-Compatible. DCS = low (AGND) to enable DCS (recommended). DCS = high (AVDD1) to disable DCS. Do Not Connect. These pins should float. CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode, and OUTPUT MODE = 1 (AVDD1) for LVDS outputs. Data Format Select Pin. CMOS control pin that determines the format of the output data. DFS = high (AVDD1) for twos complement, DFS = low (ground) for offset binary format. Set Pin for LVDS Output Current. Place 3.7 k resistor terminated to DRGND. 3.3 V (5%) Analog Supply. Reference Mode Selection. Connect to AGND for internal 1 V reference; connect to AVDD2 for external reference. 1.0 V Reference I/O--Function Dependent on SENSE. Decouple to ground with 0.1 F and 10 F capacitors. Analog Ground. The exposed heat sink on the bottom of the package must be connected to AGND. Differential Reference Output. Decoupled to ground with 0.1 F capacitor and to REFB (Pin 11) with 0.1 F and 10 F capacitors. Differential Reference Output. Decoupled to ground with a 0.1 F capacitor and to REFT (Pin 10) with 0.1 F and 10 F capacitors. 5.0 V Analog Supply (5%). Analog Input--True. Analog Input--Complement. Clock Input--True. Clock Input--Complement. Digital Output Ground. 3.3 V Digital Output Supply (3.0 V to 3.6 V). D0 Complement Output Bit (LVDS Levels). D0 True Output Bit. D1 Complement Output Bit. D1 True Output Bit. D2 Complement Output Bit. D2 True Output Bit. D3 Complement Output Bit. D3 True Output Bit. D4 Complement Output Bit. D4 True Output Bit. D5 Complement Output Bit. D5 True Output Bit. D6 Complement Output Bit. D6 True Output Bit. D7 Complement Output Bit. D7 True Output Bit. Data Clock Output--Complement. Data Clock Output--True. D8 Complement Output Bit. D8 True Output Bit. D9 Complement Output Bit. D9 True Output Bit. D10 Complement Output Bit. D10 True Output Bit. D11 Complement Output Bit. D11 True Output Bit.
Rev. PrF | Page 12 of 24
Preliminary Technical Data
Pin No. 79 80 81 82 83 84 85 86 89 90 99 Mnemonic D12- D12+ D13- D13+ D14- D14+ D15- D15+ (MSB) OR- OR+ SFDR
AD9446
Description D12 Complement Output Bit. D12 True Output Bit. D13 Complement Output. D13 True Output Bit. D14 Complement Output. D14 True Output Bit. D15 Complement Output. D15 True Output Bit. Out-of-Range Complement Output Bit. Out-of-Range True Output Bit. CMOS control pin that enables (SFDR MODE = 1) a proprietary circuit that may improve the spurious-free dynamic range (SFDR) performance of the AD9446. It is useful in applications where the dynamic range of the system is limited by discrete spurious frequency content caused by nonlinearities in the ADC transfer function. SFDR MODE = 0 for normal operation; floats low.
Rev. PrF | Page 13 of 24
AD9446
87 DRGND 88 DRVDD 97 AVDD1 96 AVDD1 95 AVDD1 94 AVDD1 93 AVDD1 100 AGND 92 AVDD1 98 AGND 91 AGND 99 SFDR
Preliminary Technical Data
76 DRVDD 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 AGND 42 AVDD1 43 AVDD1 44 AVDD1 45 AGND 46 DRGND 47 DRVDD 48 DNC 49 DNC 50 DRGND D4 D3 D2 D1 D0 DNC DCO+ DCODNC DNC DRVDD DRGND DNC DNC DNC DNC DNC DNC DNC DNC DNC DNC DNC DNC
89 D15
86 D14
85 D13
84 D12
83 D11
82 D10
90 OR
81 D9
80 D8
79 D7
78 D6
DCS MODE DNC OUTPUT MODE DFS LVDS_BIAS AVDD1 SENSE VREF AGND REFT REFB AVDD2 AVDD2 AVDD2 AVDD2 AVDD2 AVDD2 AVDD1 AVDD1 AVDD1 AGND VIN+ VINAGND AVDD2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 AVDD2 26 AVDD2 27 AVDD2 28 AVDD2 29 AVDD2 30 AVDD2 31 AVDD1 32 AVDD1 33 AVDD1 34
AD9446 Pinout
AVDD2 35
AVDD1 36
AVDD2 37
AVDD1 38
AGND 39
CLK+ 40
Figure 5. 100-Lead TQFP/EP Pin Configuration in CMOS Mode
Rev. PrF | Page 14 of 24
CLK- 41
77 D5
Preliminary Technical Data
Table 8. Pin Function Descriptions--100-Lead TQFP/EP in CMOS Mode
Pin No. 1 2, 49 to 62, 65 to 66, 69, 3 4 5 6, 18 to 20, 32 to 34, 36, 38, 43 to 45, 92 to 97 7 8 9, 21, 24, 39, 42, 46, 91, 98, 100, Exposed Heat Sink 10 11 12 to 17, 25 to 31, 35, 37 22 23 40 41 47, 63, 75, 87, 48, 64, 76, 88 67 68 70 71 72 73 74 77 78 79 80 81 82 83 84 85 86 89 90 99 Mnemonic DCS MODE DNC OUTPUT MODE DFS LVDS_BIAS AVDD1
AD9446
Description Clock Duty Cycle Stabilizer (DCS) Control Pin, CMOS-Compatible. DCS = low (AGND) to enable DCS (recommended). DCS = high (AVDD1) to disable DCS. Do Not Connect. These pins should float. CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode, and OUTPUT MODE = 1 (AVDD1) for LVDS outputs. Data Format Select Pin. CMOS control pin that determines the format of the output data. DFS = high (AVDD1) for twos complement, DFS = low (ground) for offset binary format. Set Pin for LVDS Output Current. Place 3.7 k resistor terminated to DRGND. 3.3 V (5%) Analog Supply.
SENSE VREF AGND REFT REFB AVDD2 VIN+ VIN- CLK+ CLK- DRGND DRVDD DCO- DCO+ D0(LSB) D1+ D2+ D3+ D4+ D5+ D6+ D7+ D8+ D9+ D10+ D11+ D12+ D13+ D14+ D15+ (MSB) OR+ SFDR
Reference Mode Selection. Connect to AGND for internal 1 V reference; connect to AVDD2 for external reference. 1.0 V Reference I/O--Function Dependent on SENSE. Decouple to ground with 0.1 F and 10 F capacitors. Analog Ground. The exposed heat sink on the bottom of the package must be connected to AGND. Differential Reference Output. Decoupled to ground with 0.1 F capacitor and to REFB (Pin 11) with 0.1 F and 10 F capacitors. Differential Reference Output. Decoupled to ground with a 0.1 F capacitor and to REFT (Pin 10) with 0.1 F and 10 F capacitors. 5.0 V Analog Supply (5%). Analog Input--True. Analog Input--Complement. Clock Input--True. Clock Input--Complement. Digital Output Ground. 3.3 V Digital Output Supply (3.0 V to 3.6 V). Data Clock Output--Complement. Data Clock Output--True. D0 True Output Bit. (CMOS Levels) D1 True Output Bit. D2 True Output Bit. D3 True Output Bit. D4 True Output Bit. D5 True Output Bit. D6 True Output Bit. D7 True Output Bit. D8 True Output Bit. D9 True Output Bit. D10 True Output Bit. D11 True Output Bit. D12 True Output Bit. D13 True Output Bit. D14 True Output Bit. D15 True Output Bit. Out-of-Range True Output Bit. CMOS control pin that enables (SFDR MODE = 1) a proprietary circuit that may improve the spurious-free dynamic range (SFDR) performance of the AD9446. It is useful in applications where the dynamic range of the system is limited by discrete spurious frequency content caused by nonlinearities in the ADC transfer function. SFDR MODE = 0 for normal operation; floats low.
Rev. PrF | Page 15 of 24
AD9446 EQUIVALENT CIRCUITS
AVDD2 VIN+ AVDD2 2.5pF 1k
Preliminary Technical Data
DRVDD
3.5V X1 1k SHA
DX
AVDD2
05089-006
2.5pF
Figure 6. Equivalent Analog Input Circuit
Figure 9. Equivalent CMOS Digital Output Circuit
05089-009
VIN-
VDD
DRVDD
DRVDD
1.2V LVDSBIAS 3.74k
K
DCS MODE, OUTPUT MODE, DFS 30k
05089-007
ILVDSOUT
Figure 7. Equivalent LVDS_BIAS Circuit
Figure 10. Equivalent Digital Input Circuit, DFS, DCS MODE, OUTPUT MODE
AVDD2
DRVDD
12k CLK+ 12k CLK- 150 10k 150 10k
V DX- V
V DX+ V
05089-008
05089-010
Figure 8. Equivalent LVDS Digital Output Circuit
Figure 11. Equivalent Sample Clock Input Circuit
Rev. PrF | Page 16 of 24
05089-011
Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS
AD9446
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, sample rate = 100 MSPS, LVDS mode, DCS enabled, TA = 25C, 3.2 V p-p differential input, AIN = -0.5 dBFS, internal trimmed reference (nominal VREF = 1.6 V), unless otherwise noted.
0
0
-20
-20
Signal Power (-dBFS)
-40
Signal Power (-dBFS)
-40
-60
-60
-80
-80
-100
-100
-120
-120
-140 0 6.563 13.13 19.69 26.25 32.81 39.38 45.94 52.5 Frequency (MHz)
-140 0 6.563 13.13 19.69 26.25 32.81 39.38 45.94 Frequency (MHz) 52.5
Figure 12. 32K Point Single-Tone FFT/105 MSPS/2.3 MHz
Figure 13. 32K Point Single-Tone FFT/105 MSPS/70.3 MHz
Rev. PrF | Page 17 of 24
AD9446 THEORY OF OPERATION
The AD9446 architecture is optimized for high speed and ease of use. The analog inputs drive an integrated, high bandwidth track-and-hold circuit that samples the signal prior to quantization by the 16-bit pipeline ADC core. The device includes an on-board reference and input logic that accepts TTL, CMOS, or LVPECL levels. The digital output logic levels are user selectable as standard 3 V CMOS or LVDS (ANSI-644 compatible) via the OUTPUT MODE pin.
Preliminary Technical Data
Internal Reference Trim
The internal reference voltage is trimmed during the production test to adjust the gain (analog input voltage range) of the AD9446. Therefore, there is little advantage to the user supplying an external voltage reference to the AD9446. The gain trim is performed with the AD9446's input range set to 3.2 V p-p nominal (SENSE connected to AGND). Because of this trim and the fact that the 3.2 V p-p analog input range provides maximum ac performance, there is little benefit to using analog input ranges <2 V p-p. Users are cautioned that the differential nonlinearity of the ADC varies with the reference voltage. Configurations that use <3.2 V p-p may exhibit missing codes and, therefore, degraded noise and distortion performance.
VIN+ VIN- REFT ADC CORE 0.1F 0.1F REFB VREF 10F + 0.1F SELECT LOGIC SENSE 0.5V 0.1F +
ANALOG INPUT AND REFERENCE OVERVIEW
A stable and accurate 0.5 V voltage reference is built into the AD9446. The input range can be adjusted by varying the reference voltage applied to the AD9446, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. The various reference modes are described in the next few sections.
Internal Reference Connection
A comparator within the AD9446 detects the potential at the SENSE pin and configures the reference into four possible states, which are summarized in Table 9. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 14), setting VREF to ~1.6 V. Connecting the SENSE pin to VREF switches the reference amplifier output to the SENSE pin, completing the loop and providing a ~1.0 V reference output. If a resistor divider is connected, as shown in Figure 15, the switch again sets to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as
10F
R2 VREF = 0.5 V x 1 + R1 In all reference configurations, REFT and REFB drive the A/D conversion core and establish its input span. The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference.
Figure 14. Internal Reference Configuration
VIN+ VIN- REFT ADC CORE 0.1F 0.1F REFB VREF + 10F 0.1F R2 SENSE SELECT LOGIC 0.1F +
10F
R1
0.5V
AD9446
Figure 15. Programmable Reference Configuration
Rev. PrF | Page 18 of 24
05089-042
05089-043
AD9446
Preliminary Technical Data
Table 9. Reference Configuration Summary
Selected Mode External Reference Programmable Reference Programmable Reference (Set for 2 V p-p) Internal Fixed Reference SENSE Voltage AVDD 0.2 V to VREF 0.2 V to VREF AGND to 0.2 V Resulting VREF (V) N/A
R2 (See Figure 15) 0.5 x 1 + R1 R2 , R1 = R2 = 1 k 0.5 x 1 + R1
AD9446
Resulting Differential Span (V p-p) 2 x external reference 2 x VREF 2.0 V p-p 3.2 V p-p
1.6
External Reference Operation
The AD9446's internal reference is trimmed to enhance the gain accuracy of the ADC. An external reference may be more stable over temperature, but the gain of the ADC is not likely to be improved. Figure X shows the typical drift characteristics of the internal reference in both 1 V and 0.5 V modes. When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7 k load. The internal buffer still generates the positive and negative full-scale references, REFT and REFB, for the ADC core. The input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of 1.6 V.
VIN+
1.6Vp-p 1Vp-p
VIN-
3.5V
DIGITAL OUT = ALL 1s
DIGITAL OUT = ALL 0s
05089-045
Figure 16. Differential Analog Input Range for VREF = 1.6 V
Analog Inputs
As with most new high speed, high dynamic range ADCs, the analog input to the AD9446 is differential. Differential inputs improve on-chip performance because signals are processed through attenuation and gain stages. Most of the improvement is a result of differential analog stages having high rejection of even-order harmonics. There are also benefits at the PCB level. First, differential inputs have high common-mode rejection of stray signals, such as ground and power noise. Second, they provide good rejection of common-mode signals, such as local oscillator feedthrough. The specified noise and distortion of the AD9446 cannot be realized with a single-ended analog input, so such configurations are discouraged. Contact ADI for recommendations of other 16-bit ADCs that support single-ended analog input configurations. With the 1 V reference (nominal value, see the Internal Reference Trim section), the differential input range of the AD9446's analog input is nominally 3.2 V p-p or 1.6 V p-p on each input (VIN+ or VIN-).
The AD9446 analog input voltage range is offset from ground by 3.5 V. Each analog input connects through a 1 k resistor to the 3.5 V bias voltage and to the input of a differential buffer. The internal bias network on the input properly biases the buffer for maximum linearity and range (see the Equivalent Circuits section). Therefore, the analog source driving the AD9446 should be ac-coupled to the input pins. The recommended method for driving the analog input of the AD9446 is to use an RF transformer to convert single-ended signals to differential (see Figure 18). Series resistors between the output of the transformer and the AD9446 analog inputs help isolate the analog input source from switching transients caused by the internal sample-and-hold circuit. The series resistors, along with the 1 k resisters connected to the internal 3.5 V bias, must be considered in impedance matching the transformers input. For example, if RT is set to 51 , RS is set to 33 , and there is a 1:1 impedance ratio transformer, the input will match a 50 source with a full-scale drive of 10.0 dBm. The 50 impedance matching can also be incorporated on the secondary side of the transformer, as shown in the evaluation board schematic (see Figure X and Figure X).
ANALOG INPUT SIGNAL RT ADT1-1WT RS AIN
RS
0.1F
AD9444
05089-046
AIN
Figure 17. Transformer-Coupled Analog Input Circuit
Rev. PrF | Page 19 of 24
AD9446
CLOCK INPUT CONSIDERATIONS
Any high speed ADC is extremely sensitive to the quality of the sampling clock provided by the user. A track-and-hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the A/D output. For that reason, considerable care was taken in the design of the clock inputs of the AD9446, and the user is advised to give careful thought to the clock source. Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to the clock duty cycle. Commonly a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9446 contains a clock duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. As shown in Figure X, noise and distortion performance are nearly flat for a 30% to 70% duty cycle with the DCS enabled. The DCS circuit locks to the rising edge of CLK+ and optimizes timing internally. This allows for a wide range of input duty cycles at the input without degrading performance. Jitter in the rising edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than 30 MHz nominally. The loop has a time constant associated with it that needs to be considered in applications where the clock rate can change dynamically, which requires a wait time of 1.5 s to 5 s after a dynamic clock frequency increase (or decrease) before the DCS loop is relocked to the input signal. During the time period that the loop is not locked, the DCS loop is bypassed, and the internal device timing is dependant on the duty cycle of the input clock signal. In such an application, it may be appropriate to disable the duty cycle stabilizer. In all other applications, enabling the DCS circuit is recommended to maximize ac performance. The DCS circuit is controlled by the DCS MODE pin; a CMOS logic low (AGND) on DCS MODE enables the duty cycle stabilizer, and logic high (AVDD1 = 3.3 V) disables the controller. The AD9446 input sample clock signal must be a high quality, extremely low phase noise source to prevent degradation of performance. Maintaining 16-bit accuracy places a premium on the encode clock phase noise. SNR performance can easily degrade by 3 dB to 4 dB with 70 MHz analog input signals when using a high jitter clock source. (See the TBD application note.) For optimum performance, the AD9446 must be clocked differentially. The sample clock inputs are internally biased to ~2.2 V, and the input signal is usually ac-coupled into the CLK+ and CLK- pins via a transformer or capacitors. Figure 18 shows one preferred method for clocking the AD9446. The clock source (low jitter) is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the secondary of the transformer limit clock excursions
Preliminary Technical Data
into the AD9446 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9446 and limits the noise presented to the sample clock inputs. If a low jitter clock is available, another option is to ac couple a differential ECL/PECL signal to the encode input pins, as shown in Figure 20.
CLOCK SOURCE ADT1-1WT CLK+
0.1F
AD9446
HSMS2812 DIODES
05089-047
CLK-
Figure 18. Crystal Clock Oscillator, Differential Encode
VT
0.1F
ENCODE ECL/ PECL 0.1F
AD9446
ENCODE
05089-048
VT
Figure 19. Differential ECL for Encode
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fINPUT) and rms amplitude due only to aperture jitter (tJ) can be calculated using the following equation.
SNR = 20 log[2fINPUT x tJ]
In the equation, the rms aperture jitter represents the rootmean-square of all jitter sources, which includes the clock input, analog input signal, and ADC aperture jitter specification. IF undersampling applications are particularly sensitive to jitter, see Figure 20. The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9446. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock at the last step.
Rev. PrF | Page 20 of 24
Preliminary Technical Data
75 0.2ps 70
AD9446
termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. LVDS mode facilitates interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended, with a 100 termination resistor located as close to the receiver as possible. It is recommended to keep the trace length less than 1 inch to 2 inches and to keep differential output trace lengths as equal as possible.
65 0.5ps
SNR (dBc)
60
1.0ps 1.5ps 2.0ps 2.5ps 3.0ps
55
50
CMOS Mode
In applications that can tolerate a slight degradation in dynamic performance, the AD9446 output drivers can be configured to interface with 2.5 V or 3.3 V logic families by matching DRVDD to the digital supply of the interfaced logic. CMOS outputs are available when OUTPUT MODE is CMOS logic low (or AGND for convenience). In this mode, the output data bits, DX, are single-ended CMOS as is the overrange output, OR. The output clock is provided as a differential CMOS signal, DCO+/DCO-. Lower supply voltages are recommended to avoid coupling switching transients back to the sensitive analog sections of the ADC. The capacitive load to the CMOS outputs should be minimized, and each output should be connected to a single gate through a series resistor (220 ) to minimize switching transients caused by the capacitive loading.
05089-049
45
40 1 10 100 INPUT FREQUENCY (MHz) 1000
Figure 20. SNR vs. Input Frequency and Jitter
POWER CONSIDERATIONS
Care should be taken when selecting a power source. The use of linear dc supplies is highly recommended. Switching supplies tend to have radiated components that may be received by the AD9446. Each of the power supply pins should be decoupled as closely to the package as possible using 0.1 F chip capacitors. The AD9446 has separate digital and analog power supply pins. The analog supplies are denoted AVDD1 (3.3 V) and AVDD2 (5 V), and the digital supply pins are denoted DRVDD. Although the AVDD1 and DRVDD supplies may be tied together, best performance is achieved when the supplies are separate. This is because the fast digital output swings can couple switching current back into the analog supplies. Note that both AVDD1 and AVDD2 must be held within 5% of the specified voltage. The DRVDD supply of the AD9446 is a dedicated supply for the digital outputs in either LVDS or CMOS output modes. When in LVDS mode, the DRVDD should be set to 3.3 V. In CMOS mode, the DRVDD supply may be connected from 2.5 V to 3.6 V for compatibility with the receiving logic.
TIMING
The AD9446 provides latched data outputs with a pipeline delay of TBD clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of CLK+. Refer to Figure 2 and Figure 3 for detailed timing diagrams.
OPERATIONAL MODE SELECTION
Data Format Select
The data format select (DFS) pin of the AD9446 determines the coding format of the output data. This pin is 3.3 V CMOS compatible, with logic high (or AVDD1, 3.3 V) selecting twos complement, and DFS logic low (AGND) selecting offset binary format. Table 10 summarizes the output coding.
DIGITAL OUTPUTS
LVDS Mode
The off-chip drivers on the chip can be configured to provide LVDS-compatible output levels via Pin 5 (OUTPUT MODE). LVDS outputs are available when OUTPUT MODE is CMOS logic high (or AVDD1 for convenience) and a 3.74 k RSET resistor is placed at Pin 7 (LVDSBIAS) to ground. Dynamic performance, including both SFDR and SNR, is maximized when the AD9446 is used in LVDS mode, and designers are encouraged to take advantage of this mode. The AD9446 outputs include complimentary LVDS outputs for each data bit (DX+/DX-), the overrange output (OR+/OR-), and the output data clock output (DCO+/DCO-). The RSET resistor current is multiplied on-chip, setting the output current at each output equal to a nominal 3.5 mA (11 x IRSET). A 100 differential
Output Mode Select
The OUPUT MODE pin controls the logic compatibility, as well as the pinout of the digital outputs. This pin is a CMOScompatible input. With OUTPUT MODE = 0 (AGND), the AD9446 outputs are CMOS-compatible and the pin assignment for the device is defined in Table 8. With OUTPUT MODE = 1 (AVDD1, 3.3 V), the AD9446 outputs are LVDS-compatible and the pin assignment for the device is defined in Table 7.
Duty Cycle Stabilizer
The DCS circuit is controlled by the DCS MODE pin; a CMOS logic low (AGND) on DCS MODE enables the DCS, and logic high (AVDD1, 3.3 V) disables the controller.
Rev. PrF | Page 21 of 24
AD9446
Table 10. Digital Output Coding
Code 65536 8192 8191 0 VIN+ - VIN- Input Span = 3.2 V p-p (V) 1.600 0 -0.0000488 -1.60 VIN+ - VIN- Input Span = 2 V p-p (V) 1.000 0 -0.000122 -1.00
Preliminary Technical Data
Digital Output Offset Binary (D9******D0) 1111 1111 1111 1111 1000 0000 0000 0000 0111 1111 1111 1111 00 0000 0000 0000 Digital Output Twos Complement (D9******D0) 0111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 1000 0000 0000 0000
EVALUATION BOARD
Evaluation boards are offered to configure the AD9446 in either CMOS or LVDS mode only. This design represents a recommended configuration for using the device over a wide range of sampling rates and analog input frequencies. These evaluation boards provide all the support circuitry required to operate the ADC in its various modes and configurations. Complete schematics and silk screen plots follow. Gerber files are available from applications engineering that demonstrate the proper routing and grounding techniques that should be applied at the system level. It is critical that signal sources with very low phase noise (<1 ps rms jitter) be used to realize the ultimate performance of the converter. Proper filtering of the input signal to remove harmonics and lower the integrated noise at the input is also necessary to achieve the specified noise performance. The evaluation boards are shipped with an ac to 6 V dc power supply. The evaluation boards include low dropout regulators to generate the various dc supplies required by the AD9446 and its support circuitry. Separate power supplies are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by proper connection of various jumpers (see Figure TBD).
The LVDS mode evaluation boards include an LVDS-to-CMOS translator, making them compatible with the high speed ADC FIFO evaluation kit (HSC-ADC-EVALA-SC). The kit includes a high speed data capture board that provides a hardware solution for capturing up to 32 kB of high speed ADC output data in a FIFO memory chip (user upgradeable to 256 kB). Software is provided to enable the user to download the captured data to a PC via the USB port. This software also includes a behavioral model of the AD9446 and many other high speed ADCs. Behavioral modeling of the AD9446 is also available at www.analog.com/ADIsimADC. The ADIsimADCTM software supports virtual ADC evaluation using ADI proprietary behavioral modeling technology. This allows rapid comparison between the AD9446 and other high speed ADCs, with or without hardware evaluation boards. The user may choose to remove the translator and terminations to access the LVDS outputs directly.
Rev. PrF | Page 22 of 24
AD9446 OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-026AED-HD NOTES 1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED. 2. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS. 3. THE EXPOSED HEAT SINK SOLDERED TO THE GROUND PLANE IS REQUIRED FOR THE 100-LEAD TQFP/EP.
Figure 21. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-100-1) Dimensions shown in millimeters
ORDERING GUIDE
Model AD9446BSVZ-801 AD9446BSVZ-1001 AD9446-LVDS/PCB
1
Temperature Range -40C to +85C -40C to +85C +25C
Package Description 100-Lead TQFP_EP 100-Lead TQFP_EP LVDS Mode Evaluation Board
Package Outline SV-100-3 SV-100-3
Z = Pb-free part.
Rev. PrF | Page 23 of 24
AD9446 NOTES
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05490-0-8/05(PrF)
Rev. PrF | Page 24 of 24

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